mp8042 24v, 5a dual channel power half-bridge mp8042 rev. 0.91 www.monolithicpower.com 1 5/5/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. the future of analog ic technology description the mp8042 is a configurable full-bridge or dual channel half-bridge that can be configured as the output stage of a class-d audio amplifier. each channel can be driven independently as stereo single ended audio amplifiers, or driven complementary in a bridge tied load (btl) audio amplifier configuration. the mp8042 features a low current shutdown mode, standby mode, input under voltage protection, current limit, thermal shutdown and fault flag signal output. both channels of the driver interface with standard logic signals. the mp8042 is available in a 20-pin tssop (with exposed pad) package. features ? 5a peak current output ? up to 600khz switching frequency ? protected integrated 150m ? power switches ? 30ns switch dead time ? all switches current limited ? internal under voltage protection ? internal thermal protection ? 2.1ma operating current ? fault output flag ? stereo single ended output power: 20w/channel at 24v, 4 ? load ? bridge tied load output power: 40w at 24v, 8 ? load applications ? class d audio drivers ? full or half-bridge dc-dc switching regulators ? motor drivers ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application mp8042 u1 nc agnd1 pwm1 stby pwm2 fault shdn agnd2 nc vdr2 vdr1 bst1 pgnd1 out1 vdd1 nc vdd2 out2 pgnd2 bst2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 vcc vcc vdd cn1 cn2 out1 out2 gnd pwm1 + vcc d4 d5 d7 d6 d2 1n4148 d3 1n4148 stby pwm2 fault shdn
mp8042 ?24v, 5a dual channel power half-bridge mp8042 rev. 0.91 www.monolithicpower.com 2 5/5/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. ordering information part number* package top marking free air temperature (t a ) mp8042df tssop20f mp8042df ?40 c to +85 c * for tape & reel, add suffix ?z (e.g. mp8042df?z). for rohs compliant packaging, add suffix ?lf (e.g. mp8042df?lf?z) package reference nc agnd1 pwm1 stby pwm2 fault shdn agnd2 nc vdr2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 vdr1 bst1 pgnd1 out1 vdd1 nc vdd2 out2 pgnd2 bst2 top view exposed pad absolute maxi mum ratings (1) vdd1/2 supply voltage ............................... 26v out1/2 pin voltage ............ ?0.3v to v dd + 0.3v out1/2 to bst1/2 .........................?0.3v to +6v voltage at all other pins................?0.3v to +6v continuous power dissipation (t a = +25c) (2) ??????????????????....3.1w storage temperature.............. ?55 c to +150 c junction temperature.............................150c lead temperature .................................260c recommended operating conditions (3) vdd1/2 supply voltage ...................7.5v to 24v peak output current ......................5a maximum operating junct. temp (t j )...... -40 c to +125 c thermal resistance (4) ja jc tssop20f..............................40 ....... 6 .... c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max) = (t j (max)-t a )/ ja . exceeding the maximum allowable powe r dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on approximately 1? square of 1 oz copper.
mp8042 ?24v, 5a dual channel power half-bridge mp8042 rev. 0.91 www.monolithicpower.com 3 5/5/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. electrical characteristics v dd1 = v dd2 = 12v, shdn v = 5v, t a = +25 c, unless otherwise specified. parameters symbol condition min typ max units vdd operating current i load = 0a 2.1 2.5 ma vdd shutdown current shdn v = 0v 4.0 10 a vdd operating threshold, low 5.8 6.1 v vdd operating threshold, high 6.63 7.2 v stby threshold, low 1.0 1.2 v stby threshold, high 1.85 2.0 v shdn threshold, low 1.0 1.2 v shdn threshold, high 1.9 2.0 v pwm 1,2 threshold, low 1.5 1.69 v pwm 1,2 threshold, high 1.83 2.0 v pwm input bias current 1 a out on resistance (5) v dd = 7.5v, high-side and low-side 0.15 ? v pwm = 5, sinking 5 a out current limit (5) v pwm = 0, sourcing 5 a out switching frequency v pwm = 0 to 2v, 50% duty cycle 0.6 mhz out maximum duty cycle (6) v dd = 7.5v, v pwm = 2v, c bst = 100nf, f sw = 3.3khz 99.5 % out rise/fall time (5) v pwm = 0v to 5v 10 ns pwm pulse width v pwm = 0v to 2v, high or low pulse 200 ns dead time (5) i out = 100ma 30 ns pwm to out delay time rising v pwm = 0v to 5v 37 45 ns pwm to out delay time falling v pwm = 5 to 0v 54 65 ns thermal shutdown temperature (5) t j rising, hysteresis = 20c 150 c notes: 5) not production tested. 6) out drives low for 1.5s every 300 s to charge the bst to sw capacitor.
mp8042 ?24v, 5a dual channel power half-bridge mp8042 rev. 0.91 www.monolithicpower.com 4 5/5/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. pin functions pin # name description 1 nc no connect. 2 agnd1 analog ground 1. 3 pwm1 driver logic input 1. drive pwm1 with the signal that controls the mp8042 out1. drive pwm high to turn on the high side switch; drive pwm low to turn on the low-side switch. 4 stby standby input. default low (internal pull-down ). if driven high, the output of drivers is determined by the pwm1/2. if driven low, the output of both drivers is high impedance. 5 pwm2 driver logic input 2. drive pwm2 with the signal that controls the mp8042 out2. drive pwm high to turn on the high-side switch; drive pwm low to turn on the low-side switch. 6 fault fault output. a low output at fault indicates that the mp8042 has detected an over temperature or over current condition. this output is open drain. 7 shdn shutdown input. when low, bot h channels will be shut off. 8 agnd2 analog ground 2. 9 nc no connect. 10 vdr2 gate drive supply bypass 2. the voltage at vdr2 is supplied from an internal regulator from vdd2. vdr2 powers the internal circuitry and internal mosfet gate drive for the out2 stage. bypass vdr2 to pgnd with a 0.1 f to 10 f capacitor. 11 bst2 bootstrap supply 2. bst2 powers the high-si de gate of the out2 stage. connect a 0.1 f or greater capacitor between bst2 and out2. 12 pgnd2 power ground 2. connect the exposed pad on bottom side to the ground plane. 13 out2 switched output 2. connect the output lc filt er to out2. out2 is valid approximately 100s after vdd2 goes high. 14 vdd2 power supply input 2. connect vdd2 to the pos itive side of the input power supply. bypass vdd2 to pgnd as close to the ic as possible. 15 nc no connect. 16 vdd1 power supply input 1. connect vdd1 to the pos itive side of the input power supply. bypass vdd1 to pgnd as close to the ic as possible. 17 out1 switched output 1. connect the output lc filt er to out1. out1 is valid approximately 100s after vdd1 goes high. 18 pgnd1 power ground 1. connect the exposed pad on bottom side to the ground plane. 19 bst1 bootstrap supply 1. bst1 powers the high-si de gate of the out1 stage. connect a 0.1 f or greater capacitor between bst1 and out1. 20 vdr1 gate drive supply bypass 1. the voltage at vdr1 is supplied from an internal regulator from vdd1. vdr1 powers the internal circuitry and internal mosfet gate drive for the out1 stage. bypass vdr1 to pgnd with a 0.1 f to 10 f capacitor.
mp8042 ?24v, 5a dual channel power half-bridge mp8042 rev. 0.91 www.monolithicpower.com 5 5/5/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. typical performanc e characteristics v dd1 = v dd2 = 20v, shdn v = 5v, t a = +25 c, unless otherwise specified. 100ns/div. 100ns/div. v sw 10v/div. v fault 2v/div. i l 5a/div. +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 amplitude (dbr) 10 10k 20k 1k 100 frequency (hz) input/output waveform positive pulse input/output waveform negative pulse normal switch waveform short circuit negative current short circuit positive current 100 10 1 0.1 0.01 thd+n (%) 0.01 1 0.1 10 30 p out (w) f=1khz v sw 10v/div. v out1 10v/div. v out2 10v/div. v fault 2v/div. v out1 10v/div. v pwm1 2v/div. i l 5a/div. v out1 10v/div. v pwm1 2v/div. 5ns/div. output rise-time v out1 5v/div. 5ns/div. output fall-time v out1 5v/div.
mp8042 ?24v, 5a dual channel power half-bridge mp8042 rev. 0.91 www.monolithicpower.com 6 5/5/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. typical performanc e characteristics (continued) v dd1 = v dd2 = 20v, shdn v = 5v, t a = +25 c, unless otherwise specified. standby 50ms/div. 50ms/div. shut-down start-up standby v dd 10v/div. v pwm1 5v/div. v out1 10v/div. i l 5a/div. v dd 10v/div. v pwm1 5v/div. v out1 10v/div. i l 5a/div. v stby 2v/div. v out1 10v/div. v stby 2v/div. v out1 10v/div.
mp8042 ?24v, 5a dual channel power half-bridge mp8042 rev. 0.91 www.monolithicpower.com 7 5/5/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. operation the mp8042 is a high voltage, dual channel power half- bridge that can be configured as the output of a class d amplifier. the output is in phase with the input, and the dead time is optimized for symmetrical performance, regardless of load conditions. when shutdown pin ( shdn ) is low, both channels 1 and 2 will be shut off. when the standby pin ( stby ) is pulled low, it causes the outputs of both channels to go into high impedance. however, when the voltage across the bst1/2 and out1/2 pins drops sufficiently low, the bottom mosfet is turned on to refresh the external bootstrap capacitor. for a bootstrap capacitor of 100nf, the refresh time is approximately 300ns. in order to prevent erratic operation, two under voltage lockout (uvlo) circuits are used. one of them is to ensure that the supply for the bottom gate drive circuit is sufficiently high and the other is for the top gate driver. fault protection to protect the power mosfets, two layers of protection are provided. the first is the current limit, wherein if the current through either the top or the bottom mosfet exceeds an internally preset value of 5a, that particular mosfet is immediately shut down and the complementary mosfet is turned on. if this fails to reset the current and there is an indication that the current is going to runaway, the current foldback will kick in. this ensures that the current is reset close to zero before resuming operation. thermal monitoring is also integrated into the mp8042. if the die temperature rises above 150 c, both switches are turned off. the temperature must fall below 130 c before normal operation resumes. to enhance the robustness of the device under short circuit condition, a capacitor can be connected to the fault pin, as shown in figure 1. the time constant of the rc is selected to be greater than 50ms for the fault node to reach 1v. under short circuit condition, the fault node will be reset to zero and the part will be place in standby mode until the voltage at the stby pin is above 1v. figure 1? fault protection circuit fault output the mp8042 includes an open drain, active low fault indicator output ( fault ). a fault will be indicated if the current limit is tripped or the thermal shutdown is tripped. a fault on any channel causes the fault pin to be pulled low. however, only that fault channel has its output set to high impedance. do not apply more than 6v to the fault pin.
mp8042 ?24v, 5a dual channel power half-bridge mp8042 rev. 0.91 www.monolithicpower.com 8 5/5/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. block diagram regulator vdr1 vdd1 agnd1 logic control high-side driver fault handling & control logic control fault stby shdn regulator vdr2 vdd2 agnd2 over current sense high-side driver low-side driver thermal shutdown low-side driver over current sense pwm1 out1 vdd1 pgnd1 bst1 pwm2 vdd2 out2 bst2 pgnd2 figure 2?function block diagram
mp8042 ?24v, 5a dual channel power half-bridge notice: the information in this document is subject to change wi thout notice. please contact m ps for current specifications. users should warrant and guarantee that third party intellectual property rights ar e not infringed upon when integrating mps products into any application. mps will not assume any legal responsibility for any said applications. mp8042 rev. 0.91 www.monolithicpower.com 9 5/5/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. package information tssop20f note: 1) control dimension is in inches. dimension in bracket is millimeters. see detail "a" see detail "b" 0.004(0.090) 0.008(0.200) 0.007(0.190) 0.010(0.250) 0.004(0.090) 0.006(0.160) 0.075(0.190) 0.012(0.300) detail "b" 0.047(1.200) max 0.007(0.190) 0.012(0.300) 0.032(0.800) 0.041(1.050) 0.002(0.050) 0.006(0.150) 0.252 (6.400) 0.260 (6.600) seating plane 0.0256(0.650)typ pin 1 ident. 0.169 0.177 (4.300) (4.500) 0.244 0.260 (6.200) (6.600) 0.030(0.750) 0.030(0.750) 0.105 (2.67) 0.118 (3.00) pad width 0.150 (3.80) 0.165 (4.19) pad length 0.039(1.000)ref 0.010(0.250) 0.018(0.450) 0.030(0.750) 0 o -8 o detail "a" gate plane 0.004(0.090) 0.004(0.090)
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